The present invention relates generally to fabrication of interconnects within integrated circuits, and more particularly, to minimizing resistance and electromigration of an interconnect structure by adjusting the thermal anneal temperature and the amount of dopant of an alloy seed layer of the interconnect structure.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and extruded metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
Referring to FIG. 1, a cross sectional view is shown of a copper interconnect 102 within a trench 104 formed in an insulating layer 106. The copper interconnect 102 within the insulating layer 106 is formed on a semiconductor wafer 108 such as a silicon substrate as part of an integrated circuit. Because copper is not a volatile metal, copper cannot be easily etched away in a deposition and etching process as typically used for aluminum metallization. Thus, the copper interconnect 102 is typically formed by etching the trench 104 as an opening within the insulating layer 106, and the trench 104 is then filled with copper typically by an electroplating process, as known to one of ordinary skill in the art of integrated circuit fabrication.
Unfortunately, copper is a mid-bandgap impurity in silicon and silicon dioxide. Thus, copper may diffuse easily into these common integrated circuit materials. Referring to FIG. 1, the insulating layer 106 may be comprised of silicon dioxide or a low dielectric constant insulating material such as organic doped silica, as known to one of ordinary skill in the art of integrated circuit fabrication. The low dielectric constant insulating material has a dielectric constant that is lower than that of pure silicon dioxide (SiO2) for lower capacitance of the interconnect, as known to one of ordinary skill in the art of integrated circuit fabrication.
Copper may easily diffuse into such an insulating layer 106, and this diffusion of copper may degrade the performance of the integrated circuit. Thus, a diffusion barrier material 110 is deposited to surround the copper interconnect 102 within the insulating layer 106 on the sidewalls and the bottom wall of the copper interconnect 102, as known to one of ordinary skill in the art of integrated circuit fabrication. The diffusion barrier material 110 is disposed between the copper interconnect 102 and the insulating layer 106 for preventing diffusion of copper from the copper interconnect 102 to the insulating layer 106 to preserve the integrity of the insulating layer 106.
Further referring to FIG. 1, an encapsulating layer 112 is deposited as a passivation layer to encapsulate the copper interconnect 102, as known to one of ordinary skill in the art of integrated circuit fabrication. The encapsulating layer 112 is typically comprised of a dielectric such as silicon nitride, and copper from the copper interconnect 102 does not easily diffuse into such a dielectric of the encapsulating layer 112.
Referring to FIG. 2, typically for filling the trench 104 with copper, a diffusion barrier material 121 is deposited on the sidewalls and the bottom wall of the trench 104. The diffusion barrier material 121 is similar to the diffusion barrier material 110 of FIG. 1. A seed layer 122 of copper is deposited on the diffusion barrier material 121 at the sidewalls and the bottom wall of the trench 104, and then copper is electroplated from the seed layer 122 to fill the trench 104 in an ECD (electrochemical deposition) process, as known to one of ordinary skill in the art of integrated circuit fabrication. The seed layer 122 of copper is typically deposited by a PVD (plasma-vapor-deposition) process as known to one of ordinary skill in the art of integrated circuit fabrication. With such a deposition process, referring to FIG. 2, when the aspect ratio (defined as the depth to the width) of the trench 104 to be filled with copper is relatively large (i.e., greater than 5:1), the seed layer 122 that is deposited on the sidewalls and the bottom wall of the opening 104 may have a significant overhang 124 at the top corners of the interconnect opening 104.
Referring to FIGS. 2 and 3, when copper fill 126 is plated from the seed layer 122, the copper that is plated from the overhang 124 may close off the top of the interconnect opening 104 before a center portion of the interconnect opening 104 is filled with copper to result in formation of a void 128 within the copper fill 126 toward the center of the interconnect opening 104. Such a void 128 disadvantageously increases the resistance of the interconnect and may even contribute to electromigration failure of the interconnect.
Referring to FIG. 4, to minimize the overhang 124 at the top corners of the interconnect opening 104, the seed layer of copper 122 is deposited to be thinner. However, the deposition of the seed layer 122 is not perfectly conformal when the seed layer 122 is too thin (having a thickness of hundreds of angstroms). The seed layer 122 may be discontinuous and may not form at the sidewalls and the bottom comers of the interconnect opening 104. In addition, copper may agglomerate to form discontinuous granules when the seed layer 122 is too thin. However, it is desired for the copper fill to be plated from substantially all surfaces of the interconnect opening 104 including substantially the whole surface of the sidewalls and the bottom corners of the interconnect opening 104 to prevent void formation. Nevertheless, a thinner seed layer 122 is also desired to avoid formation of the overhang 124 for the interconnect opening 104 having high aspect ratio.
As described in U.S. Pat. No. 6,181,012 to Edelstein et al., a copper alloy instead of pure copper is used for the seed layer 122. The alloy seed layer having an alloy dopant such as aluminum, tin, indium, zirconium, or titanium for example has reduced mobility from pure copper such that electromigration is minimized. In addition, such an alloy seed layer tends to agglomerate less than pure copper such that the alloy seed layer may be thinner without agglomeration than a pure copper seed layer.
Despite such advantages of using an alloy seed layer instead of a pure copper seed layer, an alloy seed layer may increase the resistance of the interconnect structure. In the prior art, such effect of increase of resistance from the alloy seed layer is deemed to be negligible. For example, column 8, lines 5-21 of U.S. Pat. No. 6,181,012 to Edelstein et al. states:
The present invention novel seed layer for depositing a copper conductor body can be formed of a copper alloy or other metals that does not contain copper . . . For instance, the seed layer may be an alloy with a higher electrical resistivity than the main conductor copper. Furthermore, the seed layer alloy may not even contain copper. As long as the cross-sectional area occupied by the seed layer is a small fraction of the entire conductor cross-sectional area, the overall line resistance will be determined by the resistivity of the main conductor and thus, not increased undesirably by the seed layer.
Thus, in the prior art, the effect of the alloy seed layer increasing the resistance of the interconnect structure is ignored because the volume of the alloy seed layer is assumed to be a negligible fraction of the entire interconnect structure. However, as integrated circuit dimensions are further scaled down to submicron dimensions, such an assumption may no longer be valid.
Accordingly, in a general aspect of the present invention, test interconnect structures are formed with a respective alloy seed layer with adjustment of parameters of the alloy seed layer and the thermal anneal process to minimize resistance and electromigration failure of an IC (integrated circuit) interconnect structure.
In a general aspect of the present invention, an IC (integrated circuit) interconnect structure is formed by filling an IC (integrated circuit) interconnect opening within an insulating layer on a semiconductor wafer. A plurality of test interconnect structures are formed with each test interconnect structure having a respective alloy seed layer deposited onto sidewalls and a bottom wall of a respective interconnect opening within an insulating layer and with a fill conductive material formed to fill the respective interconnect opening. The respective alloy seed layer of each of the test interconnect structures has a respective thickness and a respective concentration of an alloy dopant within a bulk conductive material. A respective thermal anneal process is performed at a respective thermal anneal temperature for each of the plurality of test interconnect structures. A respective resistance is measured for each of the plurality of test interconnect structures. In addition, a respective rate of electromigration failure is measured for each of the plurality of test interconnect structures.
For forming the IC interconnect structure, an alloy seed layer is deposited onto sidewalls and a bottom wall of the IC interconnect opening. The alloy seed layer within the IC interconnect opening is comprised of the bulk conductive material doped with the alloy dopant. The IC interconnect opening is filled with the fill conductive material by growing the fill conductive material from the alloy seed layer within the IC interconnect opening. A thermal anneal process is performed at a thermal anneal temperature to anneal the alloy seed layer and the fill conductive material within the IC interconnect opening.
According to one embodiment of the present invention, at least one of the thickness of the alloy seed layer, the concentration of the alloy dopant of the alloy seed layer, and the thermal anneal temperature are adjusted to a desired thickness of the alloy seed layer, a desired concentration of the alloy dopant, and a desired thermal anneal temperature to attain a desired resistance for the IC interconnect structure formed within the IC interconnect opening. The desired thickness of the alloy seed layer, the desired concentration of the alloy dopant, and the desired thermal anneal temperature for the IC interconnect structure are adjusted depending on the respective thickness of the alloy seed layer, the respective concentration of the alloy dopant, and the respective thermal anneal temperature of one of the plurality of test interconnect structures having the respective resistance that is closest to the desired resistance for the IC interconnect structure.
For example, the resistance of the IC interconnect structure is minimized when the desired thickness of the alloy seed layer, the desired concentration of the alloy dopant, and the desired thermal anneal temperature are adjusted depending on the respective thickness of the alloy seed layer, the respective concentration of the alloy dopant, and the respective thermal anneal temperature of one of the plurality of test interconnect structures having a respective resistance that is the lowest of measured respective resistances of the plurality of test interconnect structures.
In another embodiment of the present invention, at least one of the thickness of the alloy seed layer, the concentration of the alloy dopant of the alloy seed layer, and the thermal anneal temperature are adjusted to a desired thickness of the alloy seed layer, a desired concentration of the alloy dopant, and a desired thermal anneal temperature to attain a desired electromigration failure rate for the IC interconnect structure formed within the IC interconnect opening. The desired thickness of the alloy seed layer, the desired concentration of the alloy dopant, and the desired thermal anneal temperature for the IC interconnect structure are adjusted depending on the respective thickness of the alloy seed layer, the respective concentration of the alloy dopant, and the respective thermal anneal temperature of one of the plurality of test interconnect structures having the respective measured electromigration failure rate that is closest to the desired electromigration failure rate for the IC interconnect structure.
For example, the electromigration failure rate of the IC interconnect structure is minimized when the desired thickness of the alloy seed layer, the desired concentration of the alloy dopant, and the desired thermal anneal temperature are adjusted depending on the respective thickness of the alloy seed layer, the respective concentration of the alloy dopant, and the respective thermal anneal temperature of one of the plurality of test interconnect structures having a respective electromigration failure rate that is the lowest of measured respective electromigration failure rates of the plurality of test interconnect structures.
In a further embodiment of the present invention, at least one of the thickness of the alloy seed layer, the concentration of the alloy dopant of the alloy seed layer, and the thermal anneal temperature are adjusted to a desired thickness of the alloy seed layer, a desired concentration of the alloy dopant, and a desired thermal anneal temperature to attain a desired resistance and a desired electromigration failure rate for the IC interconnect structure formed within the IC interconnect opening. The desired thickness of the alloy seed layer, the desired concentration of the alloy dopant, and the desired thermal anneal temperature are adjusted depending on the respective thickness of the alloy seed layer, the respective concentration of the alloy dopant, and the respective thermal anneal temperature of one of the plurality of test interconnect structures having the respective measured resistance and the respective measured electromigration failure rate that are closest to the desired resistance and the desired electromigration failure rate for the IC interconnect structure.
For example, the present invention is used to particular advantage when such test interconnect structures indicate that with the fill conductive material being comprised of copper, the bulk conductive material of the alloy seed layer being comprised of copper, and the alloy dopant being comprised of tin (Sn) and having a concentration of about 0.3 atomic percent, the desired thickness of the alloy seed layer is about 500 angstroms, and the desired thermal anneal temperature is about 350xc2x0 Celsius. An IC interconnect structure formed with such parameters of the seed layer and such a thermal anneal temperature has a electromigration failure rate that is reduced by about a factor of 2 from an IC interconnect structure formed with a pure copper seed layer. In addition, such an IC interconnect structure has a resistance that is even lower than an IC interconnect structure formed with a pure copper seed layer.
In this manner, instead of ignoring the effect of the alloy seed layer on the resistance of the interconnect structure as in the prior art, test interconnect structures are formed to minimize the resistance and the rate of electromigration failure of the IC interconnect structure. The present invention is especially advantageous as integrated circuit dimensions are further scaled down because the volume of the alloy seed layer may no longer be a negligible fraction of the entire interconnect structure.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.